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IRS20955(S)PbF
Functional Description
Floating PWM Input
The IRS20955S accepts floating inputs, enabling
easy half-bridge implementation. V DD , CSD and IN
refer to V SS . As a result, the PWM input signal can
directly feed into IN while referencing V SS , which is
typically the midpoint between the positive and
negative DC bus voltages in a half-bridge
configuration.
The IRS20955S also accepts a non-floating input
when V SS is tied to COM.
VDD
Over-Current Protection (OCP)
The IRS20955S features over-current protection to
protect the power MOSFETs during abnormal load
conditions. The IRS20955S engages a sequence of
events when it detects the over-current condition
during high-side or low-side turn on.
As soon as either the high-side or low-side current
sensing block detects over-current:
1. The OC Latch (OCL) flips logic states and
shutdowns the outputs LO and HO.
2. The CSD pin starts discharging the external
capacitor C t .
3. When V CSD , the voltage across C t , falls
below the lower threshold V th2 , an output
signal from COMP2 resets OCL.
IN
CSD
HV
LEVEL
SHIFT
PROTECTION
4. The CSD pin starts charging the external
capacitor C t .
5. When V CSD goes above the upper threshold
V th1 , the logic on COMP1 flips and the IC
Floating Bias
VSS
Floating Input Isolation
resumes operation.
0V – 200V
COM
As long as the over-current condition exists, the IC
will repeat the over-current protection sequence.
IRS20955
Figure 5. Floating PWM Input Structure
Figure 6. Over-Current Protection Timing Chart
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